At present, CAD (Computer Aided Design) is utilized to carry out design of LSI (Large Scale Integration), and also to perform optimization and delay analysis for the post-layout circuit.
In particular, for the clock structure of a high-end LSI, a mesh architecture (see the portion M of FIG. 1) may be utilized which distributes the clock signal in a grid (mesh) pattern similar to that of a go board. Hence, the clock delay difference in the entire circuit becomes small, and the inner-chip clock delay variation due to on-chip variation is reduced. Thereby, it is possible to diminish the clock skew. However, because there are also disadvantageous aspects in wiring resource and power consumption for distributing the clock mesh to an area as large as all over the chip, a method is provided to utilize in combination a tree structure in the terminal local area close to FF (Flip Flop) and the like. For example, it is conceivable to design a circuit as shown in FIG. 1.
Herein, after the CTS (Clock Tree Synthesis) which was determined by the clock distribution netlist, not an ideal skew analysis but a skew analysis is generally made through calculating the clock with the actual delay of clock line. However, in the cases of mesh clock configuration and hierarchical layout design, an ideal skew analysis is more frequently made even after CTS. The reason is because in the case of mesh clock, in order to calculate a correct clock delay, it is necessary to implement “SPICE (Simulation Program with Integrated Circuit Emphasis)” which is a software for simulating the behavior of an electronic circuit; however, since the implementation takes time, it is often omitted. Further, in the case of hierarchical design, there are only segments of a whole mesh structure left in terms of a hierarchical design, thereby giving rise to difficulties in making an actual clock delay analysis.    [Patent Document 1] JP 2003-162561 A
As described hereinabove, in designing a circuit, it is necessary to make ideal skew (clock) analysis. However, in ideal skew analysis, if only one assumable maximum value is regarded as the skew value, the problem may occur that the analysis may become such that has an excessively great margin. For instance, in the example shown in FIG. 1, between FF1 and FF2, the skew becomes minimum because of the final stage driver branch, while between FF2 and FF3, the skew becomes greater than that between FF1 and FF2 because of the local distribution route branch. Further, between FF3 and FF4, the skew becomes even greater because of the mesh branch. In this case, the problem may occur that even though the timing analysis and the like are made with only one maximum value as the skew value, the allowable range may become of the excessively great analysis result, thereby failing to acquire preferable results.
Further, the Patent Document 1 discloses a method for timing analysis of circuits. In this method, hold time analysis is made in the processes of: specifying a clock signal branch point, calculating the delay time of clock signal from the branch point, and deriving the timing margin based on the delay time. However, with the above technology, since the timing margin is set in compliance with the delay time, a suitable timing margin cannot be set for a complicated circuit configuration. Therefore, the problem may occur that the hold time analysis comes down in precision.